In efforts to improve the operating performance of a chip, low k dielectric materials have been increasingly investigated for use as replacements for dielectric materials with higher k values. Lowering the overall k value of the dielectric layer employed in the metal interconnect layers lowers the product of resistance×capacitance (RC) of the chip and improves its performance. There are a number of concerns in using low k materials, such as being more difficult to handle than traditionally employed higher k materials, such as oxides. Also, low k dielectric materials are readily damaged by techniques used to remove photoresist materials after the patterning of a layer. Another problem with low k dielectric materials, especially porous low k dielectric materials, is their relatively low mechanical strength. This can lead to a number of concerns in the final product, since a relatively low mechanical strength makes the low k materials susceptible to delamination and scratching during chemical mechanical polishing.
For off-chip connections, bondpads are employed in integrated circuits. The monolithic integrated circuits that are manufactured using dual damascene copper metallization and low k dielectric materials may suffer from cracking of the layers of low k materials above certain structures patterned on the integrated circuits. One of the worst case structures is considered to be large metal pads, such as bondpads, separated by a relatively small gap (5-10 μm wide). This risk of cracking is increased, particularly in the uppermost low k dielectric layer, if the edges of the pads are aligned vertically in successive layers, such as in bondpads. See, for example, FIG. 1 depicting a prior art arrangement.
FIG. 1 is a top view depicting an arrangement 10 in which a plurality of bondpads 12 are provided in a dielectric layer. In this example, the bondpads 12 are made of copper or copper alloy, and the dielectric layer is made of a low k dielectric material 14. The gaps 16 between the bondpads 12 are relatively narrow, such as between 5-10 μm wide.
In a side view, three metallization layers can be seen as forming part of the metallization of the integrated circuit. In the illustrated example of the prior art in FIG. 2, the metallization layers M1-M3 (reference numerals 18, 20, 22) are vertically connected by vias 24. Also, more metal layers may be involved.
Edges 26 of the pads 12 are vertically aligned, as seen in the side view of FIG. 2. Dielectric layers, made of a low k dielectric material, are prone to cracking. This is especially true for the uppermost low k dielectric layer in which the M3 metallization layer is provided.
The cracking of the dielectric material decreases the yield of integrated circuits made with copper metallization and low k dielectrics. It also prevents an increased number of interconnect levels to be built in low k dielectric material with conventional bondpad design. The constraint on the number of interconnect levels hampers improvements in performance of future integrated circuits.